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Computer Science Colloquia

Tuesday, April 22, 2014
Lukasz Szafaryn
Advisor: Kevin Skadron
Attending Faculty: Joanne Bechta Dugan, chair; James Cohoon, Mircea Stan, and Brett Meyer (Minor Representative)

9:30 AM, Rice Hall, Rm. 504

PhD Proposal Presentation
Understanding and Optimizing Soft-Error Protection at Different Layers


The trend of continuing technology scaling and the use of aggressive power-saving features exaggerate effects that cause soft errors in circuits, such as upsets due to charged particle strikes or timing violations due to process variability. As a result, the core area devoted to protection against these effects keeps growing to maintain the same level of resiliency while requiring novel solutions to lower the footprint of resiliency features. Achieving optimal coverage at lower cost for future processor generations requires more careful determination of vulnerability as well as more efficient resiliency solutions. To address this problem, we propose a flexible cross-layer approach that evaluates a wider range of techniques, from hardware, architecture and software layers, by applying them in complementary fashion according to their best fit to specific processor functions. The proposed work will focus on illustrating challenges with the existing resiliency solutions (redundancy, ECC) as well as on evaluating novel combinations of low-overhead hardware (hardening, parity), architecture-level (data-flow integrity) and algorithm-based approaches.