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Computer Science Colloquia

Monday, December 3, 2012
Saad Arrabi
Advisor: John Lach
Attending Faculty: Benton Calhoun (Chair); Gabriel Robins, Kevin Skadron, and Mircea Stan

10:00 AM, Rice Hall, Rm. 242

PhD Proposal Presentation
Designing Vertically Integrated Dynamically Configurable Systems


In recent and future technology generations and due to the high amount of transistors residing on die, power consumption is becoming one of the main hurdles for performance advancement. This is exacerbated by the widespread use of portable electronic devices with limited energy sources but high performance expectations, as well as by the thermal issues due to denser transistors. This problem has affected almost every aspect of the chip design, enticing designers and researchers to approach this problem from every possible aspect.

In this work, we aim to approach this problem through dynamic configurability and vertical integration. Dynamic configurability is the ability to change the configuration of the system dynamically during runtime, and vertical integration is using low-level design information in high-level decisions as well as co-optimizing multiple design levels simultaneously. Using these two concepts and their various potential applications, we are hoping to alleviate the power problem significantly for a wide range of applications and systems. In our work, we will focus on designing two main systems which exemplify the potential power reduction through configurability and vertical integration. Through the steps of designing the systems, we will show the impact of several significant aspects of dynamically configurable systems, thus providing a framework for identifying potential benefits of reconfigurability and co-optimization and a framework to implement them. We focus on the granularity of the dynamic configurability and vertical integration through exposing information between a few key low design level aspects and the system level.

The first system is Panoptic Dynamic Voltage Scaling (PDVS), where we investigate adding various spatial and temporal granularities of voltage scaling to a custom digital signal processing system. We explore fine granularities that can switch the voltage of a single arithmetic component for a single cycle. The second system is Field Programmable Cora Array (FPCA) where we investigate various methods for introducing a configurable interconnect between several simple in-order cores which can morph the design into a range of different processing configurations like variable width SIMD and MIMD architectures. This work will characterize the tradeoffs of adding different levels of configurability to the systems and analyze the tradeoffs and methods for exposing circuit design information to the system level controls.

At the end of this work, and by studying the various design aspects of the PDVS and FPCA systems and their effects on the system-level potential benefits through simulations and physical measurements, we should be able to provide the main variables to consider when adding dynamic configurability and vertical integration to system designs.