Thursday, November 12, 2009
Jiayuan Meng
Chair: Jason Lawrence
Advisor:
Olsson Hall, Conference Room 236D, 11:00:00
A Ph.D. Proposal
Breaking the Memory Wall for Highly Multi-threaded Cores
ABSTRACT
Emerging applications such as computation, media processing, machine learning and data mining usually exhibit abundant parallelism. These applications motivate the design of throughputoriented many-core architectures that employ many smaller and simpler cores in the form of multi-threaded cores and are sometimes referred to as chip multithreading (CMT). Examples are Intel’s Larrabee, Sun’s Niagara, and NVIDIA’s Tesla and Fermi.
The large number of cores and hardware thread contexts, however, burden the memory system underneath --- throughput is not limited by the clock frequency, but by the limited bandwidth in data communication and limited capacity in data storage. Even worse, because both the bandwidth and storage resources may be shared by multiple processing elements (PEs), they may constantly subject to resource contention which eventually penalizes performance. We investigate data management for throughput-oriented CMTs to either reduce data movement or tolerate data movement. Our objective is to allow CMTs to achieve scalable performance along with the thread count, despite limited area and energy budget for their memory system.